Speaker
Description
Intel’s GPUs feature an unusual explicit SIMD instruction set presenting challenges for just-in-time shader compilers. Naïvely modelling Intel’s SIMD architecture artificially increases register pressure and requires expensive register allocation algorithms based on graph colouring. To improve code quality while decreasing compile time, our compiler “Jay” eschews the hardware’s native SIMD in favour of contemporary GPUs’ simpler SIMT model. Our nonlinear remapping of logical SIMT registers onto the physical SIMD register file facilitates near-linear time register allocation with an SSA-based tree scan allocator and a decoupled spiller. Compared to Intel’s existing non-SSA Linux shader compiler, our compiler reduces spilling on a collection of game shaders by 98%. Jay demonstrates the feasibility and profitability of SSA register allocation even for irregular GPU architectures and provides the foundation for Intel’s future Linux shader compilers
| Code of Conduct | Yes |
|---|---|
| In-person or virtual presentation | In-person |
