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SUMMARY:SSA-based Register Allocation for Intel GPUs
DTSTART;VALUE=DATE-TIME:20260928T180000Z
DTEND;VALUE=DATE-TIME:20260928T184500Z
DTSTAMP;VALUE=DATE-TIME:20260904T181409Z
UID:indico-contribution-527@indico.freedesktop.org
DESCRIPTION:Speakers: Alyssa Rosenzweig (Intel)\nIntel’s GPUs feature an
  unusual explicit SIMD instruction set presenting challenges for just-in-t
 ime shader compilers. Naïvely modelling Intel’s SIMD architecture artif
 icially increases register pressure and requires expensive register alloca
 tion algorithms based on graph colouring. To improve code quality while de
 creasing compile time\, our compiler “Jay” eschews the hardware’s na
 tive SIMD in favour of contemporary GPUs’ simpler SIMT model. Our nonlin
 ear remapping of logical SIMT registers onto the physical SIMD register fi
 le facilitates near-linear time register allocation with an SSA-based tree
  scan allocator and a decoupled spiller. Compared to Intel’s existing no
 n-SSA Linux shader compiler\, our compiler reduces spilling on a collectio
 n of game shaders by 98%. Jay demonstrates the feasibility and profitabili
 ty of SSA register allocation even for irregular GPU architectures and pro
 vides the foundation for Intel’s future Linux shader compilers\n\nhttps:
 //indico.freedesktop.org/event/12/contributions/527/
LOCATION:
URL:https://indico.freedesktop.org/event/12/contributions/527/
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